Is Huawei shifting from smaller transistors to scaling?

Question

Accepted Answer

Huawei is Pivoting Chip Design Strategy Towards System-Level Scaling

Huawei Technologies is shifting its chip design strategy away from solely relying on reducing transistor size towards a system-level approach focused on scaling performance through improved efficiency. This new direction, which the company refers to as the 'Tau Scaling Law', aims to enhance chip density and performance by optimising the speed at which signals and data travel within chips and computing systems. This strategic pivot is being pursued despite significant restrictions on China's access to advanced semiconductor manufacturing equipment, with Huawei targeting chip designs by 2031 that achieve a density equivalent to 1.4 nanometre (nm) processes.
Focus on Tau Scaling Law for Enhanced Performance

The core of Huawei's revised strategy lies in the 'Tau Scaling Law', a new principle that moves beyond the traditional method of making transistors smaller. This law concentrates on reducing the time required for signals and data to traverse chips and computing systems. By shortening interconnects, lowering latency, and improving data movement within the chip, Huawei aims to achieve greater performance and chip density. This approach is seen as a credible method to extract further performance gains when access to leading-edge lithography, the process used to etch smaller features onto chips, is constrained.
Targeting 1.4nm Equivalent Density by 2031

Under its new strategy, Huawei anticipates designing chips by 2031 that possess a transistor density comparable to 1.4nm manufacturing processes. This target density is significant as it is expected to approach the global frontier of advanced chipmaking by the end of the current decade. For context, Taiwan's TSMC, a leading global chip manufacturer, is currently utilising 2nm technology and plans to introduce a 1.4nm process for mass production in 2028. This indicates Huawei's ambition to align its domestically developed capabilities with leading global advancements, albeit through a different scaling methodology.
Proven Application of Tau Scaling Law

Huawei has already applied principles related to the Tau Scaling Law over the past six years, during which it has designed and mass-produced 381 chips. These chips are intended for various applications, including smartphones and AI computing. This track record suggests a practical implementation of their system-level scaling approach. Furthermore, the company has indicated that its upcoming Kirin chips, scheduled for release later this year, will incorporate an architecture known as LogicFolding. This architecture is designed to shorten internal wiring within chips, thereby significantly improving performance, demonstrating a tangible evolution of their design philosophy.
System-Level Efficiency as a Response to Sanctions

The shift towards system-level efficiency scaling is a direct response to the US trade blacklist imposed on Huawei in 2019, which has restricted its access to advanced semiconductor technologies and global contract chipmakers. As He Hui, director of semiconductor research at Omdia, noted, Huawei is moving away from a purely "node-driven scaling" to a more holistic "system-level efficiency scaling." This strategic adaptation allows Huawei to continue advancing its chip capabilities and maintain competitiveness in critical areas like AI computing, where its Ascend chip series plays a vital role in powering Chinese AI models and offering an alternative to US-based processors.

Reading history

Hide →

This history is cleared when the page is closed.

Is Huawei shifting from smaller transistors to scaling?

Loading

Was this article helpful?

Helpful

Not helpful

Report an issue

2

0

0

Share with friends